How to check correctness of your simulator

We are currently preparing a sample output. While you are waiting for samples if you can answer "yes" for all the following answers, you are mostly likely on the right track.

As you increase cache size, do you see performance improvement?
There are some outliers though.

Do you see performance improvement when you increase the rob size?
You will see a clear trend when a memory latency is reasonably long.

Do you see performance degradation when you increase KNOB_MEM_LATENCY?

Do you see performance degradation when you increase KNOB_DCACHE_LATENCY?

Do you see performance is saturated when you increase ROB, scheduler size?

Does your simulator show significant performance benefit when you enable perfect_dcache?

Do you see in order retirement debug messages for both in order scheduling and out of order scheduling when you turn on debug messages for each thread?

Do you see out of order issue debug messages for out of order scheduling when you turn on debug messages for each thread?

Do you see in order issue debug messages for in order scheduling when you turn on debug messages for each thread? You simulator should still answer the following questions:

As you increase KNOB_GHR_LENGTH from 4 to 14, do you see performance improvement? (for a long trace)

As you increase KNOB_ISSUE_WIDTH from 1 to 3, do you see IPC(1) << IPC(2) << IPC(3) ?

As you increase KNOB_ISSUE_WIDTH from 1 to 3, do you see (IPC(2) - IPC(1)) > (IPC(3)-IPC(2)) ?

Do you see IPC (inorder scheduling) < IPC (out of order scheduling) ?