School of computer science
Georgia Institute of Technology
CS4803DGC, Spring 2009
Assignment #5
Final design review time (4/21) at KACB 2344
(30 min meeting)
12:45 - 1:30 & Wilson & Whitehead
4:00 - 4:45 & Sud & Schaefer
5:30 - 6:15 & Marin, Sim
6:15 - 7:00 & Breisch & Arias
(W) 12:00-12:45 & Manatunga & Goins
(W) 3:15 - 4:00 & Kestranek & Rowland
Final Design Review
- Top design:
Instruction, data flow from the memory to the CPUs and GPU
Data and control signals
- CPU design:
pipeline stages, SMT support, fetch address calculation, branch misprediction, cache miss handling path
memory address calculation stage, vector processing units
at least 5 MUXes, register files, AULs, latches
Memory system: load/store buffers, queues
- GPU design
at least 10 ALUs
Additional features: one of the following features
- Detailed CPU pipeline design (more muxes, more adders)
- Survey of architecture design (more information from other sources)
- Detailed GPU pipeline design (more muxes and more adders)
- Detailed memory system (more queues)
- Detailed memory controller (DRAM controller)