CS6290 High-Performance Computer Architecture
Fall 2009
|
Tentative Schedule
Week |
Dates |
Topics |
Readings |
Assignments |
1 |
8/18, 8/20 |
Review pipeline, simulation
|
AppA, Ch1 |
|
  |
|
Metrics |
|
|
2 |
8/25, 8/27 |
ILP, Dependences, and register renaming |
App A, Ch2 |
|
  |
|
out of order processors |
|
|
3 |
9/1, 9/3 |
Instruction scheduling and instruction commit |
Ch2, Ch3, [MA1][MA2] |
Homework #0 (9/1) |
  |
|
|
|
|
4 |
9/8, 9/10 |
Branch prediction |
Ch2, [BP1][BP2] |
Homework #1 (9/8 class), Programming Assignment #1 (9/11 6:00 pm) |
  |
|
|
|
|
5 |
9/15, 9/17 |
cache |
AppC |
|
  |
|
|
Ch5, [CAC1][CAC2] |
Project proposal due 9/17 |
6 |
9/22,9/24 |
Memory-I |
|
Homework #2 (9/24 class) |
  |
|
|
|
|
7 |
9/29, 10/1 |
Memory-II
| |
|
  |
  |
Mid-term |
|
10/1 Midterm |
8 |
10/6, 10/8 |
Fall recess (10/6) |
|
|
  |
|
prefetcher and memory scheduler |
[MEMSCH1][MEMSCH2] |
|
9 |
10/13,10/15 |
prefetcher |
[PREF] |
|
  |
|
speculative execution/interrupt& exceptions |
AppA, Ch2 [INT], AppG |
|
10 |
10/20,10/22 |
Static exploitation of ILP & Predication and VLIW |
AppG, [PRED] |
|
  |
|
|
|
Project milestone meetings (10/23) |
11 |
10/27,10/29 |
Multi-processors and multi-threading, Multi-cores and cache coherence |
|
Homework #3 (10/27 class) |
  |
|
|
Ch 4, [MC] |
|
12 |
11/3, 11/5 |
coherencee Synchronization, consistency |
[SC] |
Programming Assignment #2 (11/4 6pm) |
  |
|
|
|
|
13 |
11/10,11/12 |
GPUs |
[TES] |
|
  |
|
|
|
|
14 |
11/17,11/19 |
GPU , Interconnection networks |
, Appendiex E |
|
  |
|
|
|
project milestone meetings (11/20) |
15 |
11/24,11/26 |
Power, |
[PWR1][PWR2][PWR3] |
|
  |
|
Thanksgiving (11/26) |
|
11/26 Thanksgiving holidays |
16 |
12/1,12/3 |
Storage, Reliability and Redundancy, Case study, Cell, LRB |
Ch 6, [LRB] |
Programming Assignment #3 (12/1 6pm) Homework #4 (12/3 class) |
  |
|
Review |
|
Project final report and presentation |
Final |
12/11 |
Final Exam |
|
|
|