CS4803PGC/CS8803PGC Design and Programming of Game Consoles

Spring 2012

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Reading List

Red Tags indicate "must read" papers. For ACM, IEEE publications, you can use LibX.

Nintendo DS

[ARM1] ARM946E-S ARM processor
[ARM2] ARM7TDMI

GPU Introduction

[7his] 7 years of Graphics
Li-Yi Wei A Crash Course on Programmable Graphics Hardware , 2007.
[TRI] Deering, M.F. Data complexity for virtual reality: where do all the triangles go? Virtual Reality Annual International Symposium, 1993., 1993 IEEE
[PERF]Cem Cebenoyan, Chapter 28. Graphics Pipeline Performance , GPU Gems.

OpenGL Design

[OG1] Mark Segal. Kurt Akeley, The Design of the. OpenGL Graphics Interface. Silicon Graphics Computer Systems.
[OG2] Mark J. Kilgard , Silicon Graphics, Realizing OpenGL: two implementations of one architecture Inc. HWWS '97 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware.

GPU Simulator

[ATT]

, ATTILA: a cycle-level execution-driven simulator for modern GPU architectures

or here

[ATT2]Victor Moya, Carlos Gonzalez, Jordi Roca, Agustin Fernandez and Roger Espasa, A Single (Unified) Shader GPU Microarchitecture for Embedded Systems , High Performance Embedded Architectures and Compilers, Lecture Notes in Computer Science, 2005, Volume 3793/2005, 286-301

Introduction to Rasterization

[RAS1]Juan Pineda, Apollo Computer Inc., Chelmsford, MA, A parallel algorithm for polygon rasterization SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques

[RAS2]Paul Haeberli and Kurt Akeley. 1990. The accumulation buffer: hardware support for high-quality rendering. In Proceedings of the 17th annual conference on Computer graphics and interactive techniques (SIGGRAPH '90)
[RAS3] Marc Olano (University of North Carolina), Trey Greer (Hewlett-Packard) Triangle scan conversion using 2D homogeneous coordinates, HWWS '97 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware.

Joel McCormack and Robert McNamara. 2000. Tiled polygon traversal using half-plane edge functions. In Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware (HWWS '00), Stephen N. Spencer (Ed.).
Anders Kugler, The Setup for Triangle Rasterization (1996) Proc 11th Eurographics Workshop Computer Graphics Hardware (1996)
Frame Buffer

[FBR]Michael F. Deering, Stephen A. Schlapp, and Michael G. Lavelle. 1994. FBRAM: a new form of memory optimized for 3D graphics. In Proceedings of the 21st annual conference on Computer graphics and interactive techniques (SIGGRAPH '94).

William R. Mark and Kekoa Proudfoot. 2001. The F-buffer: a rasterization-order FIFO buffer for multi-pass rendering. In Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware (HWWS '01).

Eugene Lapidous and Guofang Jiao. 1999. Optimal depth buffer for low-cost graphics hardware. In Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware (HWWS '99).

Satoshi Nishimura and Tosiyasu L. Kunii. 1996. VC-1: a scalable graphics computer with virtual local frame buffers. In Proceedings of the 23rd annual conference on Computer graphics and interactive techniques (SIGGRAPH '96).
Steven Molnar Combining Z-buffer Engines for Higher-Speed Rendering , in Advances in Computer Graphics Hardware III, 1998.
Whitton, M.C. Memory Design for Raster Graphics Displays IEEE Computer Graphics and Applications, 1984
Shoup, SuperPaint: an early frame buffer graphics system , IEEE Annals of the History of Computing. 2001

Early GPUs

[REA1]Kurt Akeley, Reality Engine graphics SIGGRAPH '93 Proceedings of the 20th annual conference on Computer graphics and interactive techniques

[REA2] John S. Montrym, Daniel R. Baum, David L. Dignam, and Christopher J. Migdal. InfiniteReality: a real-time graphics system , In Proceedings of the 24th annual conference on Computer graphics and interactive techniques (SIGGRAPH '97).

[TAL] Jay Torborg and James T. Kajiya. 1996. Talisman: commodity realtime 3D graphics for the PC. In Proceedings of the 23rd annual conference on Computer graphics and interactive techniques (SIGGRAPH '96)

[NEO] McCormack et al. Neon: A (Big) (Fast) Single-Chip 3D Workstation Graphics Acclerator RWL Research Report 1999.

[PIX1] Henry Fuchs, Jack Goldfeather, Jeff P. Hultquist, Susan Spach, John D. Austin, Frederick P. Brooks, Jr., John G. Eyles, and John Poulton. 1985. Fast spheres, shadows, textures, transparencies, and imgage enhancements in pixel-planes. SIGGRAPH Comput. Graph. 19, 3 (July 1985),

[PIX2]Henry Fuchs, John Poulton, John Eyles, Trey Greer, Jack Goldfeather, David Ellsworth, Steve Molnar, Greg Turk, Brice Tebbs, and Laura Israel. 1989. Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memories. In Proceedings of the 16th annual conference on Computer graphics and interactive techniques (SIGGRAPH '89).
John Eyles, Steven Molnar, John Poulton, Trey Greer, Anselmo Lastra, Nick England, and Lee Westover. 1997. PixelFlow: the realization. In Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware (HWWS '97).
John Rohlf and James Helman. 1994. IRIS performer: a high performance multiprocessing toolkit for real-time 3D graphics. In Proceedings of the 21st annual conference on Computer graphics and interactive techniques (SIGGRAPH '94)
David Kirk and Douglas Voorhies. 1990. The rendering architecture of the DN10000VS. In Proceedings of the 17th annual conference on Computer graphics and interactive techniques (SIGGRAPH '90).
James H. Clark. 1982. The Geometry Engine: A VLSI Geometry System for Graphics. In Proceedings of the 9th annual conference on Computer graphics and interactive techniques (SIGGRAPH '82).
Adam Levinthal and Thomas Porter. 1984. Chap - a SIMD graphics processor. In Proceedings of the 11th annual conference on Computer graphics and interactive techniques (SIGGRAPH '84),
Texture Memory

Paul Heckbert, Survey of Texture Mapping , IEEE Computer Graphics, 1986.
[TEX1]Ziyad S. Hakura and Anoop Gupta. 1997. The design and analysis of a cache architecture for texture mapping. In Proceedings of the 24th annual international symposium on Computer architecture (ISCA '97).

[TEX2]Homan Igehy, Matthew Eldridge, and Kekoa Proudfoot. 1998. Prefetching in a texture cache architecture. In Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware (HWWS '98), Stephen N. Spencer (Ed.).

[TEX3]Homan Igehy and Matthew Eldridge and Pat Hanrahan, Parallel texture caching. In Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware (HWWS '99)
Parallel graphics architecture

[PGA1] Matthew Eldridge, Homan Igehy, and Pat Hanrahan. 2000. Pomegranate: a fully scalable graphics architecture. In Proceedings of the 27th annual conference on Computer graphics and interactive techniques (SIGGRAPH '00).

[PGA2] Steven Molnar, Michael Cox, David Ellsworth, and Henry Fuchs. 1994. A sorting classification of parallel rendering. In ACM SIGGRAPH ASIA 2008 courses (SIGGRAPH Asia '08).

Michael Deering and David Naegle. 2002. The SAGE graphics architecture. In Proceedings of the 29th annual conference on Computer graphics and interactive techniques (SIGGRAPH '02).
Thomas W. Crockett, Parallel Rendering, 1996
Programmable GPU

[GPGPU1]Owens, J. D. Luebke, D. Govindaraju, N. Harris, M. Kruger, J. Lefohn, A. E. Purcell, T. J. , A Survey of General-Purpose Computation on Graphics Hardware COMPUTER GRAPHICS FORUM, 2007, VOL 26; NUMBER 1, pages 80-113

Blythe, D , Proceedings of the IEEE (May 2008), 96 (5), pg. 761-778 , (here also )
[CUDA1] Scalable parallel programming with CUDA, John Nickolls, Ian Buck, Michael Garland, Kevin Skadron, August 2008, SIGGRAPH '08: SIGGRAPH 2008 classes
[TES] NVIDIA Tesla: A Unified Graphics and Computing Architecture, Lindholm, E.; Nickolls, J.; Oberman, S.; Montrym, J.;Micro, IEEE, Volume 28, Issue 2, March-April 2008 Page(s):39 - 55,
Emmett Kilgariff, Randima Fernando The GeForce 6 Series GPU Architecture , GPU Gems 2
[G200] GTX200 GPU Technical Breif
Mark Peercy, Mark Segal, and Derek Gerstmann. 2006. A performance-oriented data parallel virtual machine for GPUs. In ACM SIGGRAPH 2006 Sketches (SIGGRAPH '06).

Geometry Engine

Kurt Akeley and Tom Jermoluk. 1988. High-performance polygon rendering. In Proceedings of the 15th annual conference on Computer graphics and interactive techniques (SIGGRAPH '88),
Jatin Chhugani and Subodh Kumar. 2007. Geometry engine optimization: cache friendly compressed representation of geometry. In Proceedings of the 2007 symposium on Interactive 3D graphics and games (I3D '07).
Ron Fasner, All aboard hardware T&L, Game developer, April 2000

A-Buffer

Loren Carpenter. 1984. The A -buffer, an antialiased hidden surface method. SIGGRAPH Comput. Graph. 18, 3 (January 1984), 103-108.

Norman P. Jouppi and Chun-Fa Chang. 1999. Z3: an economical hardware technique for high-quality antialiasing and transparency. In Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware (HWWS '99)
Andreas Schilling. 1991. A new simple and efficient antialiasing with subpixel masks. In Proceedings of the 18th annual conference on Computer graphics and interactive techniques (SIGGRAPH '91).
Andreas Schilling and Wolfgang StraBer. 1993. EXACT: algorithm and hardware architecture for an improved A-buffer. In Proceedings of the 20th annual conference on Computer graphics and interactive techniques (SIGGRAPH '93)
Norman P. Jouppi and Chun-Fa Chang. 1999. Z3: an economical hardware technique for high-quality antialiasing and transparency. In Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware (HWWS '99)
Kurt Akeley and Jonathan Su. 2006. Minimum triangle separation for correct z-buffer occlusion. In Proceedings of the 21st ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware (GH '06).
Jon Hasselgren and Tomas Akenine-Moller. 2006. Efficient depth buffer compression. In Proceedings of the 21st ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware (GH '06) copy

Real-time Shading

Eric Chan, Ren Ng, Pradeep Sen, Kekoa Proudfoot, and Pat Hanrahan. 2002. Efficient partitioning of fragment shaders for multipass rendering on programmable graphics hardware. In Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware (HWWS '02)
Kekoa Proudfoot, William R. Mark, Svetoslav Tzvetkov, and Pat Hanrahan. 2001. A real-time procedural shading system for programmable graphics hardware. In Proceedings of the 28th annual conference on Computer graphics and interactive techniques (SIGGRAPH '01).
More on hardware Rasterization

[RAS3]Tomas Akenine-Moller and Jacob Strom. 2003. Graphics for the masses: a hardware rasterization architecture for mobile phones. In ACM SIGGRAPH 2003 Papers (SIGGRAPH '03).

N. Gharachorloo, S. Gupta, R. F. Sproull, and I. E. Sutherland. 1989. A characterization of ten rasterization techniques. In Proceedings of the 16th annual conference on Computer graphics and interactive techniques (SIGGRAPH '89).
Steven Molnar, , High-Speed Rendering using Scan-Line Image Composition , 1990
Michael D. McCool, Chris Wales, and Kevin Moule. 2001. Incremental and hierarchical Hilbert order edge equation polygon rasterizatione. In Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware (HWWS '01).
Ray Processing

[RAY1]Sven Woop, Jorg Schmittler, and Philipp Slusallek. 2005. RPU: a programmable ray processing unit for realtime ray tracing. ACM Trans. Graph. 24, 3 (July 2005),

[RAY2]Jorg Schmittler, Sven Woop, Daniel Wagner, Wolfgang J. Paul, and Philipp Slusallek, "Realtime Ray Tracing of Dynamic Scenes on an FPGA Chip" , Graphics Hardware, 2004.
[RAY3] Real-Time Ray Tracing with CUDA
[PGH]Programming Graphics Hardware

Some Patents

US 6,724,385 Progrmmable pixel shading architecture
Before having the name of GPUs...

Frederic I. Parke. 1980. Simulation and expected performance analysis of multiple processor Z-buffer systems. SIGGRAPH Comput. Graph. 14, 3 (July 1980),
Henry Fuchs and Brian W. Johnson. 1979. An expandable multiprocessor architecture for video graphics (Preliminary Report). In Proceedings of the 6th annual symposium on Computer architecture (ISCA '79)

Henry Fuchs. 1977. Distributing a visible surface algorithm over multiple processors. In Proceedings of the 1977 annual conference (ACM '77).
James C. Michener and James D. Foley. 1978. Some Major Issues in the Design of the Core Graphics System. ACM Comput. Surv. 10, 4 (December 1978),
Others

William R. Mark and Kekoa Proudfoot. 2001. Compiling to a VLIW fragment pipeline. In Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware (HWWS '01).
Rotations and Quaternions

Ken Shoemake. 1985. Animating rotation with quaternion curves. In Proceedings of the 12th annual conference on Computer graphics and interactive techniques (SIGGRAPH '85).
F. Sebastin Grassia. 1998. Practical parameterization of rotations using the exponential map. J. Graph. Tools 3, 3 (March 1998), 29-48.

Geometric Simplication

Michael Garland and Paul S. Heckbert. 1997. Surface simplification using quadric error metrics. In Proceedings of the 24th annual conference on Computer graphics and interactive techniques (SIGGRAPH '97). ACM

Multi-resolution image methods

Lance Williams. 1983. Pyramidal parametrics. In Proceedings of the 10th annual conference on Computer graphics and interactive techniques (SIGGRAPH '83), Peter P. Tanner (Ed.).

Thomas A. Funkhouser and Carlo H. Sequin. 1993. Adaptive display algorithm for interactive frame rates during visualization of complex virtual environments. In Proceedings of the 20th annual conference on Computer graphics and interactive techniques (SIGGRAPH '93).

Kim et al. An SoC with 1.3 gtexels/s 3-D graphics full pipeline for consumer applications IEEE Journal of Solid-State Circuits, 2006.
Tomas Akenine-Moller Notes [Mobile] Graphics Hardware , 2007
GPU Performance talk by NVIDIA folks
Physics in Graphics

ParallAX: An Architecture for Real-Time Physics, ISCA 2007

XBOX 360

[XBOX1]Xbox 360 System Architecture, IEEE Micro, Vol. 26, No. 2, March-April 2006, pp. 25-37.
[XBOX2] The XBOX 360 System Architecture, HotChips 2005, August 2005
CPU architecture

[HT] Hyper-Threading Technology Architecture and Microarchitecture, Marr, D.; Binns, F.; Hill, D.; Hinton, G.; Koufaty, D.; Miller, J.; Upton, M. Intel Technology Journal, Vol. 6, No. 1, Feb. 2002
SIMD

[SIMD2] Compilation, Architectural Support, and Evaluation of SIMD Graphics Pipeline Programs on a General-Purpose CPU. Mauricio Breternitz Jr., Herbert Hum, Sanjeev Kumar. In the Proceedings of ACM/IEEE International Conference on Parallel Architecture and Compilation Techniques (PACT), New Orleans, Louisiana, September 2003.
IBM cell architecture

[CELL1] Introduction to the Cell Multiprocessor
[CELL2] Synergistic Processing in Cell's Multicore Architecture, IEEE Micro, Vol. 26, No. 2, March-April 2006, pp.10-24.
[POWER5] IBM Power5 Chip: A Dual-Core Multithreaded Processor. Ronald N. Kalla, Balaram Sinharoy, and Joel M. Tendler. IEEE Micro. 24(2), 2004
Intel Larrabee

[LRB] Larrabee: a many-core x86 architecture for visual computing, Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Pat Hanrahan, August 2008,SIGGRAPH '08: SIGGRAPH 2008 papers

Useful Links

Related Classes

Graphics Hardware in UNC by Prof. Anselmo Lastra

Graphics processing and architecture at Iowa State , Documentation about the assignments
Prof. Akeley's Graphics Course
Interactive computer graphics iby Sugih Jamin, Umich >li> CIS 565: GPU Programming and Architecture University of Pennsylvania, by Prof. Joseph Kider
GaTech's ECE4893A/CS4803MPG
UIUC's ECE498ALI: Programming Massively Parallel Processors A lot of emphasis on CUDA
MIT's 6.189 Multicore Programming Primer A lot of emphasis on Cell architecture
a nice compile from ECE4893A/CS4803MPG course
Reading list from Grpahics architectures class in Stanford

GPGPU

CUDA
OpenCL
GPGPU.org

Graphics

OpenGL.org
The Cg Tutorial
GPU Gems
GPU Gems2
GPU Gems3
AMD's Developer Program

Cell

IBM Power 5
IBM Cell programming workshop at Georgia Tech

Profiling

NVPerfHUD