CS4290/CS6290 High-Performance Computer Architecture
Fall 2010
|
Tentative Schedule
Week |
Dates |
Topics |
Readings |
Assignments |
1 |
8/24, 8/26 |
Review (quiz) pipeline
|
AppA, Ch1 |
|
  |
|
Simulation, Lab #1 |
|
|
2 |
8/31, 9/2 |
Dependences, and register renaming |
Ch2, Ch3 |
|
  |
|
out of order processors |
|
|
3 |
9/7, 9/9 |
Instruction scheduling and commit |
Ch2, Ch3, [MA1][MA2] |
Homework #0 (9/7) |
  |
|
Branch prediction |
|
Programming Assignment #1 (9/10 6:00 pm) |
4 |
9/14, 9/16 |
Branch prediction |
Ch2, [BP1][BP2] |
Homework #1 (9/21 class) |
  |
|
|
|
|
5 |
9/21, 9/23 |
cache |
AppC |
|
  |
|
|
Ch5, [CAC1][CAC2] |
Project proposal due 9/23 |
6 |
9/28,9/30 |
Memory-I DRAM |
|
Homework #2 (9/30 class) |
  |
|
|
|
|
7 |
10/5, 10/7 |
Memory-II
| |
|
  |
  |
Mid-term |
|
10/5 Midterm |
8 |
10/12, 10/14 |
prefetcher and memory scheduler |
[MEMSCH1][MEMSCH2] |
|
9 |
10/19,10/21 |
prefetcher |
Introduction to modern CPUs
[PREF] |
Paper survey list (10/21 class) |
  |
|
|
AppA, Ch2 [INT], AppG |
|
10 |
10/26,10/28 |
speculative execution/interrupt& exceptions
Static exploitation of ILP & Predication and VLIW |
AppG, [PRED] |
Programming Assignment #2 (10/29 6 pm) |
  |
|
|
|
Project milestone meeting (10/29) |
11 |
11/2,11/4 |
Multi-processors and multi-threading, Multi-cores and cache coherence |
|
Programming Assignment #2 (11/3 6 pm) |
  |
|
|
Ch 4, [MC] |
|
12 |
11/9, 11/11 |
coherencee |
|
Homework #3 (11/11 class) |
  |
|
|
|
|
13 |
11/16,11/18 |
coherencee Synchronization, consistency |
Ch4,[SC] |
paper survey progress report (11/16) |
  |
|
|
|
|
14 |
11/23,11/25 |
GPUs |
[TES] |
Thanksgivig Holidays(11/25) |
  |
|
|
|
|
15 |
11/30,12/2 |
Power, Metrics, |
[PWR1][PWR2][PWR3] |
Programming Assignment #3 (12/3 6pm) project milestone meetings (12/3) |
  |
|
|
|
|
16 |
12/7,12/9 |
Storage, Reliability and Redundancy, Case study |
Ch 6, [LRB] |
Homework #4 (12/9 class) |
  |
|
Review |
|
Paper survey report (12/7) Project final report and presentation |
Final |
TBD |
Final Exam |
|
|
|