Publications by Date Publications by Topics Topics Processor near Memory Heterogeneous Architectures Graphics Processing Units (GPUs) Mobile computing Memory Systems 3D-stacked DRAM Memory controllers Prefetching Caching Others Power Tools to help Parallel Programming Profiling Simulation and Modeling Architecture for Graph Algorithms Thread scheduling Microarchitecture Processor near Memory C. Kersey, H. Kim, S. Yalamanchili, "Cymric: A Framework for Prototyping Near-Memory Architectures," WARP 2015, 6th Workshop on Architectural Research Prototyping, Co-Located with the 42nd International Symposium on Computer Architecture, 2015 Chad Kersey, Sudhakar Yalamanchili, Hyojong Kim, Nimit Nigania, and Hyesoon Kim, "Harmonica: An FPGA-Based Data Parallel Soft Core,"The 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2014, May, 2014 (Poster) Heterogeneous Architectures Jaekyu Lee, Dong Hyuk Woo, Hyesoon Kim, and Mani Azimi, GREEN Cache: Exploiting the Disciplined Memory Model of OpenCL on GPUs," IEEE Transactions on Computers, 2015 Jieun Lim and Hyesoon Kim, "Design space exploration of memory model for heterogeneous computing, " 2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing(SBAC-PAD), Oct. 2014 Jaekyu Lee, Si Li, Hyesoon Kim, and Sudhakar Yalamanchili "Design Space Exploration of On-chip Ring Interconnection for a CPU-GPU Heterogeneous Architecture," In Journal of Parallel and Distributed Computing (JPDC), Vol. 73, Issue 12, pp. 1525-1538, December 2013 Jaekyu Lee, Si Li, Hyesoon Kim, and Sudhakar Yalamanchili "Adaptive Virtual Channel Partitioning for Network-on-Chip in Heterogeneous Architectures," In ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 18, No. 4, pp.48:1-48:28, October 2013 Jieun Lim, Hyesoon Kim, "Design Space Exploration of Memory Model for Heterogeneous Computing," ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (MSPC-2012) in conjunction with PLDI, Beijing, China, June 2012 (poster). Jaekyu Lee, Si Li, Hyesoon Kim, and Sudhakar Yalamanchili, "Design Space Exploration of On-chip Ring Interconnection for a CPU-GPU Architecture", GIT-CERCS-12-05, Georgia Institute of Technology, 2012. Jaekyu Lee and Hyesoon Kim, "TLP-Aware Cache Management Schemes for a CPU-GPU Heterogeneous Architecture", Proceedings of the 18th International Symposium on High Performance Computer Architecture (HPCA), New Orleans, LA, February 2012 Nagesh B. Lakshminarayana, Jaekyu Lee, Hyesoon Kim, and Jinwoo Shin, "DRAM Scheduling Policy for a GPGPU Architecture Based on a Potential Function", IEEE Computer Architecture Letters (CAL), Nov. 2011 Chi-Keung Luk, Sunpyo Hong, Hyesoon Kim "Qilin: Exploiting Parallelism on Heterogeneous Multiprocessors with Adaptive Mapping," MICRO 2009 , December, 2009. Graphics Processing Units (GPUs) Jen-Cheng Huang, Joo Hwan Lee, Hyesoon Kim, Hsien-Hsin S. Lee, GPUMech: GPU Performance Modeling Technique based on Interval Analysis Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Cambridge, UK, Dec. 2014 Jieun Lim, Nagesh B. Lakshminarayana, Hyesoon Kim, William Song, Sudhakar Yalamanchili, and Wonyong Sung,   "Power Modeling for GPU Architectures Using McPAT," ACM Trans. Des. Autom. Electron. Syst. 19, 3, Article 26 (June 2014) Nagesh B Lakshminarayana, Hyesoon Kim, "Spare Register Aware Prefetching for Graph Algorithms on GPUs, " The 20th International Symposium on High Performance Computer Architecture (HPCA), Orlando, Feb 2014 Jen-Cheng Huang, Lifeng Nai, Hyesoon Kim, Hsien-Hsin Lee, "TBPoint: Reducing Simulation Time for Large Scale GPGPU Kernels," IPDPS 2014, May 2014 Jaekyu Lee, Si Li, Hyesoon Kim, and Sudhakar Yalamanchili "Design Space Exploration of On-chip Ring Interconnection for a CPU-GPU Heterogeneous Architecture," In Journal of Parallel and Distributed Computing (JPDC), Vol. 73, Issue 12, pp. 1525-1538, December 2013 Jaekyu Lee, Si Li, Hyesoon Kim, and Sudhakar Yalamanchili "Adaptive Virtual Channel Partitioning for Network-on-Chip in Heterogeneous Architectures," In ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 18, No. 4, pp.48:1-48:28, October 2013 Joo Hwan Lee, Jiayuan Meng, Hyesoon Kim, "SESH framework: A Space Exploration Framework for GPU Application and Hardware Codesign," 4th International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS13), held as part of SC13, Denver, Colorado, USA, November 2013 Hyesoon Kim, "Supporting Virtual Memory in GPGPU without Supporting Precise Exceptions," ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (MSPC-2012) in conjunction with PLDI, Beijing, China, June 2012(poster). Jae Woong Sim, Aniruddha Dasgupta, Hyesoon Kim, and Richard Vuduc, "A Performance Analysis Framework for Identifying Performance Benefits in GPGPU Applications", Proceedings of the 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), New Orleans, LA, February 2012 Nagesh B. Lakshminarayana, Jaekyu Lee, Hyesoon Kim, and Jinwoo Shin, "DRAM Scheduling Policy for a GPGPU Architecture Based on a Potential Function", IEEE Computer Architecture Letters (CAL), Nov. 2011 Dongwon Lee, Marilyn Wolf, Hyesoon Kim, "Design Space Exploration of the Turbo Decoding Algorithm on GPUs," CASES, Oct. 2010. Sunpyo Hong, Hyesoon Kim, "An Integrated GPU Power and Performance Model," ISCA-37, June 2010. Nagesh B. Lakshminarayana, Hyesoon Kim "Effect of Instruction Fetch and Memory Scheduling on GPU Performance," Workshop on Language, Compiler, and Architecture Support for GPGPU, in conjunction with HPCA/PPoPP 2010, 2010. Chi-Keung Luk, Sunpyo Hong, Hyesoon Kim "Qilin: Exploiting Parallelism on Heterogeneous Multiprocessors with Adaptive Mapping," MICRO 2009 , December, 2009. Sunpyo Hong, Hyesoon Kim, "An Analytical Model for a GPU Architecture with Memory-level and Thread-level Parallelism Awareness," Proceedings of the 36th International Symposium on Computer Architecture (ISCA) , Austin, TX, June 2009. Tools to help Parallel Programming Bevin Brett, Pranith Kumar, Minjang Kim, Hyesoon Kim, "CHiP: A Profiler to Measure the effect of Cache Contention on Scalability," Workshop on Multithreaded Architectures and Applications in conjunction with IPDPS-27, Boston, USA, May 2013 Joo Hwan Lee, Kaushik Patel, Nimit Nigania, Hyojong Kim, Hyesoon Kim, "OpenCL Performance Evaluation on Modern Multi Core CPUs," Multicore and GPU Programming Models, Languages and Compilers Workshop(PLC 2013), in conjunction with IPDPS-27, Boston, USA, May 2013 Minjang Kim, Nagesh B. Lakshminarayana, Hyesoon Kim, Chi-Keung Luk, "SD3: An Efficient Dynamic Data-Dependence Profiling Mechanism," IEEE Transactions on Computers (TC), Accepted on July 2012. Minjang Kim, Pranith Kumar, Hyesoon Kim, and Bevin Brett, "Predicting Potential Speedup of Serial Code via Lightweight Profiling and Emulations with Memory Performance Model", Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium (IPDPS), Shanghai, China, May 2012 Jae Woong Sim, Aniruddha Dasgupta, Hyesoon Kim, and Richard Vuduc, "A Performance Analysis Framework for Identifying Performance Benefits in GPGPU Applications", Proceedings of the 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), New Orleans, LA, February 2012 Minjang Kim, Hyesoon Kim, Chi-Keung Luk, "SD3: A scalable Approach to Data-Dependence Profiling ," MICRO-43, Atlanta, GA, 2010. Minjang Kim, Hyesoon Kim, Chi-Keung Luk, "Prospector: A Dynamic Data-Dependence Profiler To Help Parallel Programming," (poster) HotPar-2, June, 2010. Memory Systems 3D stacked DRAM Jaewoong Sim, Alaa R. Alameldeen, Zeshan Chishti, Chris Wilkerson, Hyesoon Kim, "Transparent Hardware Management of Stacked DRAM as Part of Memory", Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Cambridge, UK, Dec. 2014 Jaewoong Sim, Gabriel Loh, Hyesoon Kim, Mike O'Connor, Mithuna Thottethodi , "A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch '' The 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-45) Vancouver, BC, Canada, Dec. 2012. Memory controllers Nagesh B. Lakshminarayana, Jaekyu Lee, Hyesoon Kim, and Jinwoo Shin, "DRAM Scheduling Policy for a GPGPU Architecture Based on a Potential Function", IEEE Computer Architecture Letters (CAL), Nov. 2011 Prefetching Nagesh B Lakshminarayana, Hyesoon Kim, "Spare Register Aware Prefetching for Graph Algorithms on GPUs, "HPCA 2014 Jaekyu Lee, Hyesoon Kim, and Richard Vuduc, "When Prefetching Works, When It Doesn't, and Why", ACM Transactions on Architecture and Code Optimization (TACO) Jaekyu Lee, Nagesh B Lakshminarayana, Hyesoon Kim, Richard Vuduc, "Hardware and Software Prefetching Mechanisms for GPGPU," MICRO-43, Atlanta, GA, 2010. Santhosh Srinath, Onur Mutlu, Hyesoon Kim, and Yale N. Patt, "Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers," Proceedings of the 13th International Symposium on High-Performance Computer Architecture (HPCA), Phoenix, AZ, February 2007 Caching Jaekyu Lee, Dong Hyuk Woo, Hyesoon Kim, and Mani Azimi, GREEN Cache: Exploiting the Disciplined Memory Model of OpenCL on GPUs," IEEE Transactions on Computers, 2015 Jaewoong Sim, Jaekyu Lee, Moinuddin K. Qureshi, and Hyesoon Kim, "FLEXclusion: Balancing Cache Capacity and On-chip Bandwidth with Flexible Exclusion", Proceedings of the 39th IEEE International Symposium on Computer Architecture (ISCA), Portland, OR, June 2012 Jaekyu Lee, Si Li, Hyesoon Kim, and Sudhakar Yalamanchili, "Design Space Exploration of On-chip Ring Interconnection for a CPU-GPU Architecture", GIT-CERCS-12-05, Georgia Institute of Technology, 2012. Jaekyu Lee and Hyesoon Kim, "TLP-Aware Cache Management Schemes for a CPU-GPU Heterogeneous Architecture", Proceedings of the 18th International Symposium on High Performance Computer Architecture (HPCA), New Orleans, LA, February 2012 Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt, "Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References," International Journal of Parallel Programming (IJPP), Vol. 33, No. 5, pages 529-559, October 2005. Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt, "Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance," Proceeedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), pages 2-9, Foz Do Iguacu, PR, Brazil, October 2004. Others Onur Mutlu, Hyesoon Kim, and Yale N. Patt, "Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses," IEEE Transactions on Computers (TC), Vol. 55, No.12, pages 1491-1508, December 2006. Onur Mutlu, Hyesoon Kim, and Yale N. Patt, "Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance" IEEE Micro, Special Issue: Micro's Top Picks from Microarchitecture Conferences (MICRO TOP PICKS), Vol. 26, No. 1, pages 10-20, January/February 2006. Submitted final version Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt, "An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors," IEEE Transactions on Computers (TC), Vol. 54, No. 12, pages 1556-1571, December 2005. Onur Mutlu, Hyesoon Kim, and Yale N. Patt, "Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns," Proceedings of the 38th International Symposium on Microarchitecture (MICRO), pages 233-244, Barcelona, Spain, November 2005. One of the five papers nominated for the Best Paper Award by the Program Committee. An extended version as HPS Technical Report, TR-HPS-2006-004, University of Texas at Austin, April 2006. Onur Mutlu, Hyesoon Kim, and Yale N. Patt, "Techniques for Efficient Processing in Runahead Execution Engines," Proceedings of the 32nd International Symposium on Computer Architecture (ISCA), pages 370-381, Madison, WI, June 2005. One of the 13 computer architecture papers of 2005 selected as Top Picks by IEEE Micro. Onur Mutlu, Hyesoon Kim, Jared Stark, and Yale N. Patt, "On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor," IEEE Computer Architecture Letters (CAL), Vol. 4, January 2005. Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt, "Understanding the Effects of Wrong-Path Memory References on Processor Performance," Proceedings of the 3rd Workshop on Memory Performance Issues (WMPI), pages 56-64, An extended version as HPS Technical Report, TR-HPS-2005-001, University of Texas at Austin, January 2005. Power Jieun Lim, Nagesh B. Lakshminarayana, Hyesoon Kim, William Song, Sudhakar Yalamanchili, and Wonyong Sung,   "Power Modeling for GPU Architectures Using McPAT," ACM Trans. Des. Autom. Electron. Syst. 19, 3, Article 26 (June 2014) Nagesh B Lakshminarayana, Hyesoon Kim, "Block-Precise Processors: Low-Power Processors with Reduced Operand Store Writes and Result Broadcasts," Fourth Workshop on Energy-efficient Design (WEED 2012) in conjunction with ISCA, Portland, Oregon, June 2012 Sunpyo Hong, Hyesoon Kim, "An Integrated GPU Power and Performance Model," ISCA-37, June 2010. Nagesh B. Lakshminarayana, Hyesoon Kim, "Understanding Performance, Power and Energy Behavior in Asymmetric Multiprocessors," 2008 IEEE International Conference on Computer Design (ICCD), Oct 2008. ( Nominated for the Best Paper Award by the Program Committee.) Profiling Joo Hwan Lee, Jiayuan Meng, Hyesoon Kim, "SESH framework: A Space Exploration Framework for GPU Application and Hardware Codesign," 4th International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS13), held as part of SC13, Denver, Colorado, USA, November 2013 Bevin Brett, Pranith Kumar, Minjang Kim, Hyesoon Kim, "CHiP: A Profiler to Measure the effect of Cache Contention on Scalability," Workshop on Multithreaded Architectures and Applications in conjunction with IPDPS-27, Boston, USA, May 2013 Joo Hwan Lee, Kaushik Patel, Nimit Nigania, Hyojong Kim, Hyesoon Kim, "OpenCL Performance Evaluation on Modern Multi Core CPUs," Multicore and GPU Programming Models, Languages and Compilers Workshop(PLC 2013), in conjunction with IPDPS-27, Boston, USA, May 2013 Minjang Kim, Hyesoon Kim, Chi-Keung Luk, "SD3: A scalable Approach to Data-Dependence Profiling ," MICRO-43, Atlanta, GA, 2010. Hyesoon Kim, M. Aater Suleman, Onur Mutlu, and Yale N. Patt, "2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set," Proceedings of the 4th International Symposium on Code Generation and Optimization (CGO), pages 159-169, New York, NY, March 2006. An extended version as HPS Technical Report, TR-HPS-2006-001, University of Texas at Austin, January 2006. Mobile computing Dilan Manatunga, Hyesoon Kim, and Saibal Mukhopadhyay, "SP-CNN: A Scalable and Programmable CNN-based Accelerator," Micro, IEEE, 2015 Hyojong Kim, Hongyeol Lim, Dilan Manatunga, Hyesoon Kim, Gi-Ho Park, Accelerating Application Start-up with Nonvolatile Memory in Android Systems ," Micro, IEEE, Jan/Feb, 2015 Dilan Manatunga, Joo Hwan Lee, Hyesoon Kim, "Hardware Support for Safe Execution of Native Client Applications," Computer Architecture Letters, vol.PP, no.99, pp.1,1, 2014 Chayong Lee, Euna Kim, and Hyesoon Kim , "The AM-Bench: An Android Multimedia Benchmark Suite", GIT-CERCS-12-04, Georgia Institute of Technology, 2012. Simulation and Modeling Jen-Cheng Huang, Joo Hwan Lee, Hyesoon Kim, Hsien-Hsin S. Lee, GPUMech: GPU Performance Modeling Technique based on Interval Analysis Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Cambridge, UK, Dec. 2014 Jen-Cheng Huang, Lifeng Nai, Hyesoon Kim, Hsien-Hsin Lee, "TBPoint: Reducing Simulation Time for Large Scale GPGPU Kernels," IPDPS 2014 May 2014 Arun Rodrigues, Keren Bergman, David Bunde, Elliott Cooper-Balis, Kurt Ferreira, Scott Hemmert, Brian Barrett, Robert Hendry, Bruce Jacob, Hyesoon Kim, Vitus Leung, Michael Levenhagen, Mitchelle Rasquinha, Rolf Riesen, Paul Rosenfeld, Maria Del Carmen Ruiz Varela, Sudhakar Yalamanchili and Cassandra Versaggi, "Improvements to the Structural Simulation Toolkit," 5th International ICST Conference on Simulation Tools and Techniques (SIMUtools 2012), Desenzano, Italy, Mar. 2012. Jae Woong Sim, Aniruddha Dasgupta, Hyesoon Kim, and Richard Vuduc, "A Performance Analysis Framework for Identifying Performance Benefits in GPGPU Applications", Proceedings of the 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), New Orleans, LA, February 2012 Sunpyo Hong, Hyesoon Kim, "An Integrated GPU Power and Performance Model," ISCA-37, June 2010. Sunpyo Hong, Hyesoon Kim, "An Analytical Model for a GPU Architecture with Memory-level and Thread-level Parallelism Awareness," Proceedings of the 36th International Symposium on Computer Architecture (ISCA) , Austin, TX, June 2009. Architecture for Graph Algorithms Lifeng Nai, Yinglong Xia, Ilie G. Tanase, Hyesoon Kim, and Ching-Yung Lin, "GraphBIG: Understanding Graph Computing in the Context of Industrial Solutions," The International Conference for High Performance Computing, Networking, Storage and Analysis(SC), 2015 Nagesh B Lakshminarayana, Hyesoon Kim, "Spare Register Aware Prefetching for Graph Algorithms on GPUs, " The 20th International Symposium on High Performance Computer Architecture (HPCA), Orlando, Feb 2014 Thread scheduling Nagesh B. Lakshminarayana, Hyesoon Kim "Effect of Instruction Fetch and Memory Scheduling on GPU Performance," Workshop on Language, Compiler, and Architecture Support for GPGPU, in conjunction with HPCA/PPoPP 2010, 2010. Nagesh B. Lakshminarayana, Jaekyu Lee, Hyesoon Kim, "Age Based Scheduling Policy for Asymmetric Multiprocessors," Super Computing , November, 2009. Nagesh B. Lakshminarayana, Hyesoon Kim, "Understanding Performance, Power and Energy Behavior in Asymmetric Multiprocessors," 2008 IEEE International Conference on Computer Design (ICCD), Oct 2008. ( Nominated for the Best Paper Award by the Program Committee.) Nagesh Lakshminarayana, Sushma Rao, Hyesoon Kim, "Asymmetry Aware Scheduling Algorithms for Asymmetric Multiprocessor," Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA), in conjunction with the 35th International Symposium on Computer Architecture, Beijing, China, June 2008. Microarchitecture Nagesh B. Lakshminarayana and Hyesoon Kim, "Block-Precise Processors: Low-Power Processors with Reduced Operand Store Accesses and Result Broadcasts," IEEE Transactions on Computers, 2015 Dilan Manatunga, Joo Hwan Lee, Hyesoon Kim, "Hardware Support for Safe Execution of Native Client Applications," Computer Architecture Letters, vol.PP, no.99, pp.1,1, 2014 Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert S. Cohn, "VPC Prediction:Very Low Cost Indirect Branch Prediction using Conditional Branch Prediction Hardware" , IEEE Transactions on Computers (TC) , Vol 58, No.9, pages 1153-1170, 2009. José A. Joao, Onur Mutlu, Hyesoon Kim, Rishi Agarwal, and Yale N. Patt, "Improving the Performance of Object-Oriented Languages with Dynamic Predication of Indirect Jumps" Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Seattle, WA, March 2008. Chang Joo Lee, Hyesoon Kim, Onur Mutlu, and Yale N. Patt, "Performance-Aware Speculation Control using Wrong Path Usefulness Prediction" Proceedings of the 14th International Symposium on High-Performance Computer Architecture (HPCA), Salt Lake City, UT, February 2008. Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert S. Cohn, "VPC Prediction: Reducing the Cost of Indirect Branches via Hardware-Based Dynamic Devirtualization," Proceedings of the 34th Annual International Symposium on Computer Architecture (ISCA), San Diego, CA, June 2007 José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt, "Dynamic Predication of Indirect Jumps," IEEE Computer Architecture Letters(CAL), Vol. 6, May 2007 Hyesoon Kim, José A. Joao, Onur Mutlu, and Yale N. Patt, "Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors," Proceedings of the 5th International Symposium on Code Generation and Optimization (CGO), San Jose, CA, March 2007. Hyesoon Kim, José A. Joao, Onur Mutlu, and Yale N. Patt, "Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication" IEEE Micro, Special Issue: Micro's Top Picks from 2006 Computer Architecture Conferences (MICRO TOP PICKS), January/February 2007. Hyesoon Kim, José A. Joao, Onur Mutlu, and Yale N. Patt, "Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths," Proceedings of the 39th International Symposium on Microarchitecture (MICRO), Orlando, FL, December 2006. One of the 11 computer architecture papers of 2006 selected as Top Picks by IEEE Micro. Hyesoon Kim, Onur Mutlu, Jared Stark, and Yale N. Patt, "Wish Branches: Enabling Adaptive and Aggressive Predicated Execution" IEEE Micro, Special Issue: Micro's Top Picks from Microarchitecture Conferences (MICRO TOP PICKS), Vol. 26, No. 1, pages 48-58, January/February 2006. Submitted final version Hyesoon Kim, Onur Mutlu, Jared Stark, and Yale N. Patt, "Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution," Proceedings of the 38th International Symposium on Microarchitecture (MICRO), pages 43-54, Barcelona, Spain, November 2005. One of the 13 computer architecture papers of 2005 selected as Top Picks by IEEE Micro. David N. Armstrong, Hyesoon Kim, Onur Mutlu, and Yale N. Patt, "Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery," Proceeedings of the 37th International Symposium on Microarchitecture (MICRO), pages 119-128, Portland, OR, December 2004. An extended version as HPS Technical Report, TR-HPS-2004-002, University of Texas at Austin, June 2004.